(a) Field of the Invention
The present invention relates to a plasma display device including a plasma display panel (PDP), and a driving method thereof.
(b) Description of the Related Art
A PDP is a flat panel display that uses plasma generated by gas discharge to display characters or images. It includes, depending on its size, more than several scores to millions of pixels arranged in a matrix pattern.
Generally, in a driving method of a plasma display device, one frame is divided into a plurality of subfields, and the subfields are controlled by time division to thus represent gray scales. Each subfield includes a reset period, an address period, and a sustain discharge period. The reset period is for initializing the status of each discharge cell so as to facilitate an addressing operation on the discharge cell. The address period is for selecting turn-on/turn-off cells, which are the cells that must be turned on or turned off to display the intended image, and for accumulating wall charges on the turn-on cells that are addressed to be turned on. The sustain period is for causing the cells to either continue discharge to display an image on the addressed cells, or to remain inactive.
When respective operations (reset, address, sustain operations) are performed in the respective periods, capacitance exists on the panel since a discharge space between a scan electrode and a sustain electrode, and a discharge space between a surface on which an address electrode is formed and a surface on which scan and sustain electrodes are formed, operate as capacitive loads (hereinafter, referred to as “panel capacitors”). Hence, reactive power for generating a predetermined voltage in view of the capacitance is needed in addition to power for applying waveforms for addressing. Hence, an address driving integrated circuit includes a power recovery circuit for recovering the reactive power and re-using the same, as disclosed from the power recovery circuit by L. F. Weber in U.S. Pat. Nos. 4,866,349 and 5,081,400.
However, when the power recovery circuit is used to apply an address voltage Va to the address electrode in the address period, a time for a voltage of the panel capacitor to reach the voltage Va is delayed and a time for maintaining the voltage Va is shorter as compared to a case when directly applying the address voltage Va to the address electrode. Therefore, not only is an address discharge delayed, but also a light waveform is reduced.
In FIG. 1A and FIG. 1B, the amplitude of respective light waveforms La1 and La2 in respective cases is shown when the power recovery circuit is used to apply the address voltage Va to the address electrode and when address voltage Va is directly applied to the address electrode in the address period. As can be seen in FIG. 1A, when the power recovery circuit is used the address discharge is delayed to time t1 and the light waveform is also reduced to La1.
Accordingly, using the power recovery circuit problematically causes a high probability of address discharge error in the address period.
In addition, wall charge distribution, previous to the address period, formed by applying the driving waveform of the plasma display device, varies according to the temperature of the PDP. More specifically, when the temperature of the PDP is higher or lower than a reference temperature range, the probability for misfiring in the address period becomes very high since wall charges in a plasma state are unstable.